Compatibility mode code segments are executed in emulation mode, unless they have been translated by the Object Code Translator (OCT).
Emulation of an instruction can be described in the following way:
Fetch the instruction at the current program counter (CMPC).
Emulate that instruction with NM precision architecture instructions.
Update the program counter to point at the next instruction.
Note that multiple NM Precision Architecture
instructions must be executed during the
emulation of every single CM instruction. Besides the obvious cost of fetching
and emulating the instruction, there is usually additional, less obvious
overhead, such as indirection and indexing, and
updating STATUS register bits (that is, condition code, carry).
CM Object Code
CM Instructions
+-------------+
| PROC+%0 |
| PROC+%1 |
| PROC+%2 |
| PROC+%3 |
P > | PROC+%4 | ----> Fetch PUSH S-2,X
| PROC+%5 |
| PROC+%6 |
| PROC+%7 |
| PROC+%10 |
| PROC+%11 |
| PROC+%12 |
| PROC+%13 |
| PROC+%14 |
| PROC+%15 |
| PROC+%16 |
+-------------+
|
