EPIC Parallelism

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Execution and Decode Logic

Compiler

Chip

• Pipelined Scalar RISC

  • Job broken into regular pieces
  • Pipeline stages run in parallel

• Superscalar RISC

  • Multiple parallel pipelines
  • Hardware schedules instructions and evaluates potential conflicts every cycle

• EPIC (Merced & beyond)

  • Large number of functional units
  • Compiler schedules instructions and guarantees independence

Execution and

Decode Logic

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Scheduling (b)

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