RISC Parallelism

Execution and

Decode Logic

Compiler

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Scheduling (b)

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• Pipelined Scalar RISC

  • Job broken into regular pieces
  • Pipeline stages run in parallel

• Superscalar RISC

  • Multiple parallel pipelines
  • Hardware schedules instructions and evaluates potential conflicts every cycle

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• Functional unit area grows linearly with number of units.

• Scheduler area grows as the square of the number of units.

• Cost-performance reaches a point of diminishing returns

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