Parallelism Limiters and EPIC Solution

• Complexity of multiple pipelines too great to allow.effective on-chip scheduling for parallel operation

  • Solution: Explicit Parallelism (compiler handles scheduling and communicates this to the chip)..

• Number of registers on chip limits parallelism

  • Solution: quadruple registers from 32 to 128.by increasing addressing from 5 bits to 7..

• Large (and growing) Memory Latency

  • Solution: Speculative Loads..

• Conditional and/or Unpredictable Branches

  • Solution: Prediction and Predication orchestrated.by the compiler

I1

I2

I3

I4

Dependencies

Branches

I1

I2

I3

I4

Compiler

Chip

RISC

EPIC

32 to 128 Registers

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