Processor Evolution
EPIC, IA-64
Superscalar RISC
~
2 instructions / cycle
Performance
Time
RISC
<
1 instruction / cycle
.3 ins / cycle
Next generation
CISC
20-30% increase per year due
to advances in underlying
semiconductor technology
1 micron - > .5 micron --> .35 micron --> .25 micron --> .18 micron --> .13 micron
Previous slide
Next slide
Back to first slide
View graphic version
Author
|
Title
|
Track
|
Home
Send email to Interex
or to the
Webmaster
©Copyright 1999
Interex
. All rights reserved.