HPlogo System Debug Reference Manual > Chapter 4 System Debug Command Specifications

DR

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E0201 Edition 4 ♥
E0300 Edition 3
E0692 Edition 3

Displays contents of the CM or NM registers.

Syntax


   DR [cm_register] [base]
   DR [nm_register] [base]

Parameters

cm_register

The CM register to be displayed. This can be the:

DB

The stack base relative word offset of DB.

DBDST

The DB data segment number.

DL

The DL register word offset, DB relative.

CIR

The current instruction register.

CMPC

The full logical CM program counter address.

MAPDST

The CST expansion mapping data segment number.

MAPFLAG

The CST expansion mapping bit.

Q

The Q register word offset, DB relative.

S

The S register word offset, DB relative.

SDST

The CM stack data segment number.

STATUS

The CM status register.

X

The X (index) register.

If cm_register is omitted, all of the above CM registers are displayed.

nm_register

The NM register to be displayed.

If no value is provided, all NM registers are displayed (excluding the floating-point registers). The ENVL ,FP command displays all of the floating-point registers at once.

To fully understand the use and conventions for the various registers, refer to the Precision Architecture and Instruction Reference Manual (09740-90014) and Procedure Calling Conventions Reference Manual (09740-90015). (These may be ordered as a set with the part number 09740-64003.) The Procedure Calling Conventions Reference Manual is of particular importance for understanding how the language compilers utilize the registers to pass parameters, return values, and hold temporary values.

The following tables list the native mode registers available within System Debug. Many registers have aliases through which they may be referenced. Alias names in italics are not available in System Debug.

Access rights abbreviations are listed below. PM indicates that privileged mode (PM) capability is required.

d

Display access

D

PM display access

m

Modify access

M

PM modify access

The following registers are known as the General Registers.

Table 4-1 General Registers

Name Alias Access Description
R0nonedA constant 0
R1nonedmGeneral register 1
R2nonedmUsed to hold RP at times
R3nonedmGeneral register 3
[vellip]
R22nonedmGeneral register 22
R23ARG3dmArgument register 3
R24ARG2dmArgument register 2
R25ARG1dmArgument register 1
R26ARG0dmArgument register 0
R27DPdMGlobal data pointer
R28RET1dmReturn register 1
R29RET0dmReturn register 0
SLdmStatic link
R30SPdMCurrent stack pointer
R31MRPdmMillicode return pointer

The following registers are pseudo-registers. They are not defined in the Precision Architecture, but are terms used in the procedure calling conventions document and by the language compilers. They are provided for convenience. They are computed based on stack unwind information. They may not be modified.

Table 4-2 Psuedo-Registers

Name Alias Access Description
RPnonedReturn pointer (not the same as R2)
PSPnonedPrevious stack pointer

The following registers are known as the Space Registers. Registers SR4 through SR7 are used for short pointer addressing:

Table 4-3 Space Registers

Name Alias Access Description
SR0nonedmSpace register 0
SR1SARGdmSpace register argument
SRETdmSpace return register
SR2nonedmSpace register 2
SR3nonedmSpace register 3
SR4nonedMProcess local code space (tracks PC space)
SR5nonedMProcess local data space
SR6nonedMOperating system data space 1
SR7nonedMOperating system data space 2

The following registers are known as the Control Registers. They contain system state information.

Table 4-4 Control Registers

Name Alias Access Description
CR0RCTRdMRecovery counter
CR8PID1dMProtection ID 1 (16 bits)
CR9PID2dMProtection ID 2 (16 bits)
CR10CCRdMCoprocessor configuration (8 bits)
CR11SARdmShift amount register (5 bits)
CR12PID3dMProtection ID 3 (16 bits)
CR13PID4dMProtection ID 4 (16 bits)
CR14IVAdMInterrupt vector address
CR15EIEMdMExternal interrupt enable mask
CR16ITMRdMInterval timer
CR17PCSFdMPC space queue front
nonePCSBdMPC space queue back
CR18PCOFdMPC offset queue front
nonePCSBdMPC offset queue back
nonePCQFdMPC queue (PCOF.PCSF) front
nonePCQBdMPC queue (PCOB.PCSB) back
nonePCdMPCQF with priv bits set to zero.
nonePRIVdMLow two order bits (30,31) of PCOF.
CR19IIRdMInterrupt instruction register
CR20ISRdMInterrupt space register
CR21IORdMInterrupt offset register
CR22IPSWdMInterrupt processor status word
PSWdMProcessor status word
CR23EIRRdMExternal interrupt request register
CR24TR0dMTemporary register 0
[vellip]
CR31TR7dMTemporary register 7

NOTE: The Precision Architecture and Instruction Reference Manual refers to the PC (program counter) registers as the IA (instruction address) registers. This manual will use the PC mnemonic when referring to the IA registers.

The following registers are floating-point registers. If a machine has a floating-point coprocessor board, these values are from that board. If no floating-point hardware is present, the operating system emulates the function of the hardware; in that case these are the values from floating-point emulation.

Table 4-5 Floating Point Registers
Name Alias Access Description
FP0nonedmFP register 0
FP1nonedmFP register 1
FP2nonedmFP register 2
FP3nonedmFP register 3
FP4FARG0dmFP argument register 0
FRETdmFP return register
FP5FARG1dmFP argument register 1
FP6FARG2dmFP argument register 2
FP7FARG3dmFP argument register 3
FP8nonedmFP register 8
[vellip]
FP15nonedmFP register 15
FPSTATUSnonedmFP status reg(left half of FP0)
FPE1nonedmFP exception reg 1 (right half of FP0)
FPE2nonedmFP exception reg 2 (left half of FP1)
FPE3nonedmFP exception reg 3 (right half of FP1)
FPE4nonedmFP exception reg 4 (left half of FP2)
FPE5nonedmFP exception reg 5 (right half of FP2)
FPE6nonedmFP exception reg 6 (left half of FP3)
FPE7nonedmFP exception reg 7 (right half of FP3)

base

Specifies the base used to display the register data.

% or OCTAL

Octal representation

# or DECIMAL

Decimal representation

$ or HEXADECIMAL

Hexadecimal representation

ASCII

ASCII representation

This parameter can be abbreviated to as little as a single character.

Examples


   %cmdebug > dr
   DBDST=%132    DB=%1000   X=%102    STATUS=%140075=(MItroc CCG 075)
   SDST=%132     DL=%650    Q=%1006   S=%1007   CMPC=PROG %12.2046
   SEG =%12      P=%2046    CIR=%000700   MDST=%0
Display the contents of all CM registers. 

   %cmdebug > dr status
   STATUS=%022002=(miTRoC CCE 002)
Display the contents of the CM status register. 

 $nmdebug > dr

 R0 =00000000 00464800 005a6e48 00000000 R4 =00000000 00000000 00000000 00000000
 R8 =00000000 00000000 00000000 00000000 R12=00000000 00000000 00000000 00000000
 R16=00000000 00000000 00000000 0000002a R20=00000006 00007fff ffff8000 400524a8
 R24=400524a0 00000400 40052058 c0080008 R28=00000000 00000000 40052520 0000003f

 IPSW=0006ff0f=jthlnxbCVmrQPDI PRIV=0000 SAR=0010 PCQF=a.5a6e48   a.5a6e4c

 SR0=0000000a 00000057 00000017 00000000 SR4=0000000a 00000057 0000000a 0000000a
 TR0=007ea040 0080a040 0000000a 007727c0 TR4=40052848 400526a8 00bba1e0 00bba228

 PID1=0020=0010(W) PID2=0000=0000(W)     PID3=0000=0000(W) PID4=0000=0000(W)
 RCTR=ffffffff ISR=00000057 IOR=4005250c IIR=6bc23fd9 IVA=001cb000 ITMR=5b8b1e69
 EIEM=ffffffff EIRR=00000000 CCR=0000
Display all NM registers. 

   $nmdebug > dr pcqb
   PCQB=0000000a.0021d7b8
Display the contents of "pcq back". 

   $nmdebug > dr pid2
   PID2=$0004=0002(W)
Display the contents of protection ID register number 2.

Limitations, Restrictions

Floating-point registers are displayed as 64-bit long pointers. No interpretation of the data is attempted.



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