Chapter 5 Pseudo-Instruction Set

In addition to the PA-RISC instruction set, which is described in PA-RISC 1.1 Architecture and Instruction Set Reference Manual and PA-RISC 2.0 Architecture, the Assembler provides a number of pseudo-instructions that perform commonly used forms of the basic instructions. These pseudo-instructions are listed with their standard-instruction format in Table 5-1 “Pseudo-Instructions ”.




	NOTE: When coding branch instructions, including those with nullification specified, pay attention to the instruction that follows the branch in the source code. All branch instructions consider this following instruction to be in their delay slot. You can use a `NOP` pseudo-instruction to fill the delay slot when there is no other useful work to be performed. This delay slot is usually executed.

Table 5-1 Pseudo-Instructions

Pseudo-Instruction Format		Standard Instruction Format
`ADDB,cond,n`^[1]^,^[2]	`r1,r2,target`	`ADDBT,cond,n` `ADDBF,cond,n`	`r1,r2,target` `r1,r2,target`
`ADDIB,cond,n`^[1]^, ^[2]	`r1,r2,target`	`ADDIBT,cond,n` `ADDIBF,cond,n`	`r1,r2,target` `r1,r2,target`
`B`	`w`	`BL`	`w, %r0`
`COMB,cond,n`^[1]^, ^[2]	`r1,r2,target`	`COMBF,cond,n` `COMBT,cond,n`	`r1,r2,target` `r1,r2,target`
`COMIB,cond,n`^[1]^, ^[2]	`r1,r2,target`	`COMIBF,cond,n` `COMIBT,cond,n`	`r1,r2,target` `r1,r2,target`
`COPY`	`r,t`	`LDO`	`0(r),t`
`LDI`	`i,t`	`LDO`	`i(%r0),t`
`MTSAR`	`r`	`MTCTL`	`r,%cr11`
`NOP`		`OR`	`%r0,%r0,%r0`
^[1]The `cond` completer determines the actual instruction that the Assembler uses in the conditional branch. The `T` form is used with nonnegated completers. The `F` form is used with negated completers. See Table 5-2 “Compare and Branch Conditions (COMB and COMIB) ” and Table 5-3 “Add and Branch Conditions (ADDB and ADDIB)” for details. ^[2]`n` indicates an optional nullification completer.

Table 5-2 Compare and Branch Conditions (COMB and COMIB)

cond	Description
	never
`=`	`opd1` is equal to `opd2`
`<`	`opd1` is less than `opd2` (signed)
`<=`	`opd1` is less than or equal to `opd2` (signed)	Nonnegated
`<<`	`opd1` is less than `opd2` (unsigned)
`<<=`	`opd1` is less than or equal to `opd2` (unsigned)
`SV`	`opd1` minus `opd2` results in overflow (signed)
`OD`	result of `opd1` minus `opd2` is odd
`TR`	always
`<>`	`opd1` is less than or greater than `opd2`
`>=`	`opd1` is greater than or equal to `opd2` (signed)
`>`	`opd1` is greater than `opd2` (signed)	Negated
`>>=`	`opd1` is greater than or equal to `opd2` (unsigned)
`>>`	`opd1` is greater than `opd2` (unsigned)
`NSV`	`opd1` minus `opd2` results in no overflow (signed)
`EV`	result of `opd1` minus `opd2` is even

Table 5-3 Add and Branch Conditions (ADDB and ADDIB)

cond	Description
	never
`=`	`opd1` is equal to `-opd2`
`<`	`opd1` is less than `-opd2` (signed)
`<=`	`opd1` is less than or equal to `-opd2` (signed)	Nonnegated
`NUV`	`opd1` + `opd2` < `2³²` (no unsigned overflow)
`ZNV`	`opd1` + `opd2` < `2³²` or `opd1` + `opd2` = `0`
`SV`	`opd1` plus `opd2` results in overflow (signed)
`OD`	result of `opd1` plus `opd2` is odd
`TR`	always
`<>`	`opd1` is not equal to `-opd2`
`>=`	`opd1` is greater than or equal to `-opd2` (signed)
`>`	`opd1` is greater than `-opd2` (signed)	Negated
`UV`	`opd1` + `opd2` > = `2³²` (unsigned overflow)
`VNZ`	`opd1` + `opd2` > `2³²` and `opd1` + `opd2` not = `0`
`NSV`	`opd1` plus `opd2` results in no overflow (signed)
`EV`	result of `opd1` plus `opd2` is even

Chapter 5 Pseudo-Instruction Set

Technical documentation

» Table of Contents

» Index