Machine instructions usually require one or more operands.
These operands tell the processor what data to use and where
to store the result. Operands can identify a register, a location
in memory, or an immediate constant (that is, data that is coded
into the instruction itself). The operation code determines how
many and what kinds of operands are required.
Registers used in operands should be either predefined register
symbols (with the %
prefix) or user-defined register symbols defined with the .REG
directive. They can also be absolute expressions. See “Registers and Register Mnemonics” in this chapter.
The following example shows a few machine instructions with
register operands:
SCRATCH .REG %r18 ;define register SCRATCH
ADD %r3,%r7,%r4 ;r3 + r7 -> r4
OR %r7,%r3,%r8 ;inclusive or of r7,r3 -> r8
COPY SCRATCH,%r7 ;copy r18 to r7
MTCTL %r2,%sar ;set shift amount register (cr11)
MFSP %sr4,%r10 ;fetch contents of sr4
|
Operands designating memory locations usually consist of an
expression and a general register used as a base register. Some
instructions also require a space register designation. In general,
such operands are written in the form expr(sr,gr)
or expr(gr),
as in the following examples:
local_off .EQU -64
LDW 4(%dp),%r2
STW %r0,local_off-4(%sp)
LDW 0(%sr3,%r2),%r9 |
Notice that the space register can be omitted on instructions
that allow short addressing, as in the STW
instruction shown above.
If only one register is given, it is assumed to be the general
register, and the space register field in the machine instruction
is set to zero, which indicates short addressing.
The expression in a memory operand is either absolute or relocatable.
Absolute expressions are meaningful when the base register contains
the address of an array, record, or the stack pointer to which a
constant offset is required. Relocatable expressions are meaningful
when the base register is %r0,
or when the base register contains the left part of a 32-bit address
as illustrated in the following example:
LDIL L%glob,%r1 ;set up %r1 for STW
STW %r9,R%glob(%r1) |
Immediate operands provide data for the machine language instruction
directly from the bits of the instruction word itself. A few instructions
that use immediate operands are shown below:
ADDIL L%var,%dp
LDIL L%print,%r1
ADDI 4,%r3,%r5
SUBI 0x1C0,%r14,%ret0 |
Completers are special flags that modify an instruction's
behavior. They are written in the opcode field, separated from the
instruction mnemonic by a comma. The most common type of completer
is a condition test. Many instructions can conditionally trap or
nullify the following instruction, depending on the result of their
normal operation. For example, notice the completers in the sequence
below:
ADD,NSV %r1,%r2,%r3
BL,N handle_oflo,%r0
OR %r3,%r4,%r5 |
The ,NSV
in the ADD instruction
nullifies the BL
instruction if no overflow occurs in the addition operation, and
execution proceeds with the OR
instruction. If overflow does occur, the BL
instruction is executed, but the ,N
completer on the BL
specifies that the OR
instruction in its delay slot should not be
executed.
Each class of machine instructions defines the set of completers
that can be used.
These are described in the PA-RISC 1.1 Architecture
and Instruction Set Reference Manual and in PA-RISC
2.0 Architecture.
