Registers and Register Mnemonics

PA-RISC processors have four sets of registers:

Data is loaded from memory into general or floating-point registers and stored into memory from general or floating-point registers. Arithmetic and logical operations are performed on the contents of the general registers. On PA-RISC 1.0 or 1.1 each general register is 32 bits wide. On PA-RISC 2.0 each general register is 64 bits wide. On PA-RISC 2.0W (true 64-bit environment) each general register is 64 bits wide.

There are 32 general registers, denoted as %r0 through %r31. General register %r0 is special because "writes" into it are ignored, and it always reads as zero. The remaining general registers can be used normally, with the caution that %r1 is the implicit target register for the ADDIL instruction, %r31 is the implicit link register for the BLE instruction, and for PA-RISC 2.0 only, %r2 is the implicit link register for the BLVE instruction. Certain general registers also have predefined conventional uses. Refer to Table 2-7 “Register Procedure Calling Conventions”. You can find detailed information on both 32-bit and 64-bit runtime architecture under the topic PA-RISC Architecture at http://www.software.hp.com/STK/.

PA-RISC 1.0 machines have 16 floating-point registers; PA-RISC 1.1, 2.0, and 2.0W (true 64-bit environment) machines have 32 floating-point registers. Each register is capable of holding either a single- or double-precision floating-point number in IEEE format. These registers are denoted %fr0 through %fr15 for PA-RISC 1.0 and %fr0 through %fr31 for PA-RISC 1.1, 2.0, and 2.0W.

Registers %fr1, %fr2, and %fr3 are exception registers and are not available to the programmer. Floating-point register %fr0 contains a permanent floating-point zero when used in an arithmetic operation; when written or read with floating-point loads or stores, the floating-point status register is actually accessed.

In addition, on PA-RISC 1.1, 2.0. and 2.0W the left and right halves of the floating-point registers can be accessed as separate single-precision registers by using an L or R suffix.

For example, %fr8R accesses the right-most 32 bits of %fr8 as a single-precision number.

The L or R suffixes can only be used on the predefined floating-point registers in the form %frnn, where nn is the register number. It is not legal to use L or R with an integer value. For example, %fr8R is legal; 8R is not legal.

The space registers form the basis of the virtual memory system. Each of the eight space registers can hold a 16- or 32-bit space identifier, depending on the hardware model. The space registers are denoted as %sr0 through %sr7. Space register %sr0 is set implicitly by the BLE instruction, and space registers %sr5 through %sr7 cannot be modified except by code running at the most privileged level.

The control registers contain system-state information. There are 25 control registers, denoted as %cr0 and %cr8 through %cr31. Of these registers, only %cr11 (%sar), the shift amount register, and %cr16 (%itmt), the interval timer, are normally accessible to the user-level programmer. The other registers are accessed only by code running at the most privileged level.

Register operands are denoted by register-typed constants because the Assembler needs to be able to differentiate between general registers, space registers, floating point registers, and ordinary integer constants.

To make assembly code more readable, you can use the .REG directive to declare a symbolic name as an alias for a predefined register. The predefined registers have a register type associated with them. The Assembler enforces register type checking and issues a warning message if the wrong kind of register is used within an operand. A warning is also issued when an integer constant or absolute expression is found where a register is expected. You must use the .REG directive to define symbolic register names. If a symbolic name defined in an .EQU directive is used where a register symbol is expected, the Assembler issues a warning message, because it considers an .EQU defined symbol to be a simple integer constant.

	NOTE: If an absolute expression is used instead of a register or register-typed symbol name, the Assembler issues warning message number 41. This warning can be suppressed with the -w41 command-line option. Future versions of the Assembler may not always allow an absolute expression where a register is expected.

The following example demonstrates the correct usage of the .REG directive:

tblptr    .REG   %r20
aka_tbl   .REG   tblptr

Predefined registers are shown in the following tables. All of the mnemonics begin with the % character, so they do not conflict with any programmer-defined symbols.

Some additional predefined register mnemonics are provided in Table 2-7 “Register Procedure Calling Conventions” to match the standard procedure-calling convention. This is discussed briefly in Chapter 3 “HP-UX Architecture Conventions”. You can find detailed information on both 32-bit and 64-bit calling conventions under the topic PA-RISC Architecture at URL: http://www.software.hp.com/STK/.

In addition, there is a special register mnemonic defined as %previous_sp, that allows access to the previous value of the stack pointer.

%previous_sp must be used in the position of a base register; it can be used only between .ENTER and .LEAVE pseudo-operations. %previous_sp is the same as %sp unless the current .PROC has a large frame (that is, .CALLINFO specified FRAME > 8191) or .CALLINFO specified .ALLOCA_FRAME. In those two cases, %previous_sp is the same as %r3, and %r3 is set up by the .ENTER pseudo-operation.