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Expressions

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Arithmetic expressions are often valuable in writing assembly code. The Assembler allows expressions involving integer constants, symbolic constants, and symbolic addresses. These terms can be combined with the standard arithmetic operators shown in Table 2-8 “Standard Arithmetic Operators” or with bit-wise operators shown in Table 2-9 “Bit-Wise Operators”.

Table 2-8 Standard Arithmetic Operators

Operator

Operation

+

Integer addition

-

Integer subtraction

*

Integer multiplication

/

Integer division (result is truncated)

 

The multiplication and division operators have precedence over addition and subtraction. That is, multiplications and divisions are performed first from left to right, then additions and subtractions are performed from left to right. Therefore, the expression 2+3*4 evaluates to 14.

Table 2-9 Bit-Wise Operators

Operator

Operation

|

Logical OR

&

Logical AND

~

Unary logical complement (tilde)

 

Expressions produce either an absolute or a relocatable result. Any operation involving only absolute terms yields an absolute result. Relocatable terms are allowed only for the + and - operators. The legal combinations involving relocatable terms are shown in Table 2-10 “Legal Combinations For Relocatable Terms”.

Table 2-10 Legal Combinations For Relocatable Terms

Operation

Result

Absolute + Relocatable

Relocatable

Relocatable + Absolute

Relocatable

Relocatable - Absolute

Relocatable

Relocatable - Relocatable (defined locally)

Absolute

 

For more information on the term relocatable, refer to “Assembler Features”.

NOTE: The combination "relocatable-relocatable+relocatable" is not permitted.

For example, assume the symbols MONTH and YEAR are relocatable, and JANUARY and FEBRUARY are absolute. The expressions MONTH+JANUARY and MONTH+FEBRUARY-4 are relocatable, while the expressions YEAR-MONTH and FEBRUARY-4 are absolute. The expression MONTH+JANUARY*4 is also legal and produces a relocatable result, because JANUARY*4 is evaluated first, producing an absolute intermediate result that is added to MONTH. The expression MONTH+YEAR is illegal, because the sum of two relocatable terms is not permitted.

Because all instructions are a single word in length, it is not possible to form a complete 32-bit address in a single instruction. Therefore, it is likely that the Assembler (or linker) may not be able to insert the final address of a symbol into the instruction as desired. For example, to load the contents of a word into a register, the following instruction could be used:

LDW       START,%r2

Because LDW provides only 14 bits for the address of START, the Assembler or linker prints an error message if the address of START requires more than 14 bits. There are two instructions, LDIL and ADDIL, whose function is to form the left-most 21 bits of a 32-bit address. The succeeding instruction, by using the target of the LDIL or ADDIL as a base register, needs only 11 bits for the remainder of the address. The Assembler provides special operators, called field selectors, that extract the appropriate bits from the result of an expression. With the field selectors L' and R', the previous example can be recoded as follows:

LDIL      L'START,%r1            ;put left part into r1
LDW R'START(%r1),%r2 ;add r1 and right part

The field selectors are always applied to the final result of the expression. They cannot be used in the interior of an expression. Table 2-11 “Available Field Selectors” shows all the available field selectors and their meanings.

Table 2-11 Available Field Selectors

Field Selector

Meaning

F' or F%

Full 32 bits (default).

L' or L%

Right-justified, high-order 21 bits.

R' or R%

Low-order 11 bits.

LS' or LS%

High-order 21 bits after rounding to nearest multiple of 2048.

RS' or RS%

Low-order 11 bits, sign extended.

LD' or LD%

Right-justified, high-order 21 bits after rounding to next multiple of 2048.

RD' or RD%

Low-order 11 bits, with negative sign.

LR' or LR%

L% value with constant rounded to nearest multiple of 8192.

RR' or RR%

R% value with constant rounded to nearest multiple of 8192, plus the difference of the constant and the rounded constant.

T' or T%

F% value offset of data linkage table slots from linkage table pointer. In 32-bit mode, the linkage table pointer is %r19. In 64-bit mode, the linkage table pointer is %r27.

LT' or LT%

LR% value offset of data linkage table slots from linkage table pointer. In 32-bit mode, the linkage table pointer is %r19. In 64-bit mode, the linkage table pointer is %r27.

RT' or RT%

RR% value offset of data linkage table slots from linkage table pointer. In 32-bit mode, the linkage table pointer is %r19. In 64-bit mode, the linkage table pointer is %r27.

Q' or Q%

F% value offset of procedure linkage table slots from linkage table pointer. In 32-bit mode, the linkage table pointer is %r19. In 64-bit mode, the linkage table pointer is %r27.

LRQ' or LRQ%

LR% value offset of procedure linkage table slots from linkage table pointer. In 32-bit mode, the linkage table pointer is %r19. In 64-bit mode, the linkage table pointer is %r27.

RRQ' or RRQ%

RR% value offset of procedure linkage table slots from linkage table pointer. In 32-bit mode, the linkage table pointer is %r19. In 64-bit mode, the linkage table pointer is %r27.

P' or P%

Data procedure label (plabel) constructor.

LP' or LP%

Code procedure label (plabel) constructor used in LDIL instruction.

RP' or RP%

Code procedure label (plabel) constructor used in LD0 instruction.

N' or N%

A null field selector, which is applied to an LDO instruction to allow a three-instruction sequence.

NL' or NL%

Right-justified, high-order 21 bits; allows a three-instruction sequence.

NLD' or NLD%

Right-justified, high-order 21 bits after rounding to next multiple of 2048; allows a three-instruction sequence.

NLR' or NLR%

L% value with constant rounded to nearest multiple of 8192; allows a three-instruction sequence.

NLS' or NLS%

High-order 21 bits after rounding to nearest multiple of 2048; allows a three-instruction sequence.

 

On PA-RISC 1.0, the page size is 2048 bytes long; on PA-RISC 1.1, 2.0, and 2.0W the page size is 4096. The selectors L', LS', and LD' modulate by 2048, and the corresponding selectors R', RS', and RD' extract the offset relative to that address.

The distinction is whether the offset is always positive and between 0 and 0x7ff (L'-R'), always negative and between -0x800 and -1 (LD'-RD'), or between -0x400 and 0x3ff (LS'-RS'). This distinction is only important when using short addressing near a quadrant boundary, because only the left part is used to select a space register. Each pair is designed to work together just as L' and R' do in the previous example. See “Spaces”. The LR' and RR' prefixes are used for accessing different fields of a structure, allowing the sharing of the LR' computation.

For shared libraries, the field selectors T', LT', RT', Q', LRQ', and RRQ' are used in conjunction with the position-independent code options +z or +Z.

The field selectors P', LP', and RP' are used to form plabels (procedure labels) for use in dynamic calls. With position-independent code, the use of plabel values, rather than simple code addresses, is required. Refer to the HP-UX Linker and Libraries Online User Guide and ELF 64 Object File Format, http://www.software.hp.com/STK/ for more information.

For example, to get a procedure label for foo, use the following code:

ADDIL   LTP'foo,%r27,%r1   ;get left portion of plabel pointer.
LDO RTP'foo(%r1),%r4 ;add right portion to form a complete
; plabel pointer.

The field selectors in the above example can also be written LP% and RP%.

Parenthesized Subexpressions

The constant term of an expression may contain parenthesized subexpressions that alter the order of evaluation from the precedence normally associated with arithmetic operators. For example:

LABEL1-LABEL2+((6765+(2048-1))/2048)*2048

contains a parenthesized subexpression that rounds a value up to a multiple of 2048.

Absolute symbols may be equated to constant terms containing parenthesized subexpressions as in the following sequence:

BASE    .EQU    0x200
N_EL .EQU 24
SIZE .EQU (BASE+4)*N_EL
NOTE: The use of parentheses to group subexpressions may cause ambiguities in statements where parenthesized register designators are also expected.
© 1998 Hewlett-Packard Development Company, L.P.