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3.3 The Floating-Point Coprocessor Status Register

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Within the floating-point coprocessor status register (fr0), the state of the rounding mode (bits 21-22) and exception trap enable bits (bits 27-31) are guaranteed to be preserved across calls. An exception to this convention is made for any routine which is defined to explicitly modify the state of the rounding mode or the trap enable bits on behalf of the caller.

The states of the compare bit (bit 5), the delayed trap bit (bit 25), and the exception trap flags (bits 0-4) are not guaranteed to be preserved across calls.



3.2 Other Register Conventions

3.4 Summary of Dedicated Register Usage