HP 3000 Manuals HP 3000 Manuals
HP Precision Architecture HP Precision Architecture-RISC (PA-RISC), which forms the basis of the HP 3000 900 Series systems, delivers major price and performance advantages over traditional, more complex architectures, and provides the expandability to meet user requirements into the next century. PA-RISC represents a fundamental change in computer design. This new architecture is based on reduced instruction set computing concepts, with significant OLTP extensions for COBOL applications, high-performance I/O, and high availability. RISC is the result of the discovery that computer performance can be greatly increased by reducing and simplifying the computer's instruction set. This allows computer instructions to be implemented directly in hardware, eliminating the system overhead associated with the microcode of conventional computers. PA-RISC can be implemented in a number of technologies and is ideal for very large scale integration (VLSI) design. By eliminating the chip space required for microcode, highly integrated VLSI designs can be achieved, resulting in single-chip CPUs and single board processors. Pipelining, which provides higher performance by overlapping the execution of multiple instructions, is enhanced through the uniformity of the PA-RISC instructions, which enables one instruction to be executed every CPU clock cycle. Improved performance also results from the hierarchical memory design of the PA-RISC architecture and the use of optimizing compilers. Optimizing compilers generate very efficient object code, allocate registers, and schedule instruction sequences to maintain an efficient pipeline operation. Frequently used instructions and data are stored in a large number of CPU registers, thereby minimizing memory accesses. Additionally, a large amount of CPU cache provides high-speed buffering for code and data, further minimizing the time that the processor must wait while memory accesses are performed. PA-RISC transparently supports a 48- or 64-bit virtual memory address space. The 48-bit space is more than 65,000 times larger than that of a conventional 32-bit system, and the 64-bit space is more than four billion times larger. The large virtual addressing capability of the 900 Series systems allows users to expand their program sizes substantially without being limited by addressing capacity. PA-RISC has been specifically designed to easily support multiprocessing, and the high-end Series 980/200 system implements two-way symmetric multiprocessing. PA-RISC also provides for a variety of coprocessors to meet specific computing requirements. For example, 900 Series systems use hardware floating-point coprocessors to accelerate the performance of applications that use floating-point data types for scientific, engineering, or statistical applications. The simplicity of PA-RISC translates into significantly reduced design and development time, reliability, and reduced manufacturing costs. It allows simplified system designs that require substantially fewer system components than complex instruction set computer architectures. The benefit to you is industry-leading price/performance, minimal environmental requirements, and extremely reliable systems. PA-RISC is on the leading edge in computer design. It is the wave of the future and represents a significant contribution to the computer industry. The HP 3000 900 Series was the first computer in the industry to deliver the benefits of RISC to the commercial marketplace and continues to provide leadership price/performance.