HP 3000 Manuals HP 3000 Manuals
HP 3000 High-End Systems Series 955, 960, 980/100, and 980/200 The HP 3000 PA-RISC high-end systems are designed for high-performance online transaction processing (OLTP) and overall system throughput. These systems provide mainframe-class performance, support hundreds of online users, support large memory and large I/O configurations, and use an operating system that has been especially designed for PA-RISC to provide very high performance in OLTP and batch environments, while maintaining the HP 3000's ease of use. The HP 3000 offers powerful systems management and operations capabilities, high availability and backup options, tools for performance measurement and monitoring, and built-in features to ensure the highest degree of data integrity. The HP 3000 high-end systems take full advantage of advanced technology to provide exceptional performance implemented with single-chip CPUs on single-board processors. The HP 3000 900 Series high-end system family is designed to provide easy board upgrades to more powerful processors with minimal impact on end users and systems operations.Figure 2-1. HP 3000 Series 955, 960, and 980 System Package High-performance All HP 3000 high-end systems run the same, easy-to-use MPE/XL operating system, as do the other members of the broad HP 3000 business computer family. This combination of PA-RISC and MPE/XL makes the HP 3000 900 Series the industry leader in price/performance, as proven by the results of the Transaction Processing Council's TPC-A benchmark. The 900 Series complements high-performance with high availability of the system and its resources, systems management to keep the system running efficiently, networking, and high-end peripherals to meet the demands of high-volume environments. High availability begins with the high-reliability and reduced complexity Precision Architecture-RISC. Warranty data shows that the HP 3000 900 Series has achieved a greater than 50 percent increase in reliability over the industry-acknowledged, highly reliable HP 3000 Series 70. The 900 Series also provides powerfail recovery and transaction management as standard features. Transaction management automatically recovers system structures, user files, and databases after system failures. The high-end systems offer optional high-speed and online backup solutions, auto-restart after software failure, mirrored disks, and system processing unit (SPU) switchover to a secondary SPU. The 900 Series supports a complete set of networked systems management solutions, including performance monitoring and analysis, administration and configuration, system security, system availability, operations control, and storage management. To meet the demands of interoperability, the high-end 900 Series systems support the ISO distributed application service standards, ARPA Telnet, IBM SNA, and IEEE 802.3 and Ethernet LANs. High-end peripherals on the 900 Series include the HP Rewritable Optical Disk, which stores up to 20 Gbytes, or up to 70 Gbytes with software data compression provided by HP TurboSTORE/XL. Alternative to traditional mainframes. More and more mainframe application solutions are being ported to the HP 3000 900 Series high-end systems. On top of mainframe performance, powerful functionality, high availability, integrated systems and network management, and high-end peripherals, the 900 Series high-end delivers superior cost-of-ownership. By providing significantly lower hardware, software, and staffing costs compared with typical mainframe systems, HP 3000s are ideal candidates for offloading applications and replacing installed-base (older technology) mainframes. On the HP 3000 application development and maintenance is simpler and requires reduced programmer support, compared with other systems in its class. With the 900 Series' extended large addressing, programmers do not have to segment their programs or use extra data segments, which improves productivity. The HP 3000's virtual addressing capabilities can meet business application needs throughout the 1990s. The HP 3000 high-end systems requires only a fraction of the systems and operations staff needed to run and maintain traditional mainframe systems. Powerful systems management capabilities include high-capacity devices and data compression for unattended backup. Automatic, unattended error logging and restart upon software failure ensures maximum user availability and minimize delays for operator identification and response. Integrated network management capabilities for remote console, exception-based alarms, and a graphical network map provide centralized systems management control. Major features * Single chip VLSI CPU, single-board processor * HP PA-RISC * High-speed CPU cache for data and instructions * Advanced instruction pipelining * Floating-point coprocessor standard * Up to 64-bit virtual addressing: over 4 billion 2-Gbyte spaces * Translation Lookaside Buffer (TLB) for virtual to physical address translation * Battery backup, automatic powerfail recovery standard * Low cooling and power requirements; compact packaging * High-speed, average 100-Mbyte per second System Memory Bus * IEEE 802.3 or Ethernet local area network (LAN) terminal connection; HP EtherTwist LAN is also supported * HP AdvanceNet networking solutions * MPE/XL operating system Configuration Maximums 955 S960 980/100 980/200 ----------------------------------------------------------------------------------------- Performance x 955 1.0 1.4 2.4 3.7 ----------------------------------------------------------------------------------------- Memory (Mbytes) 96-256 128-256 192-512 256-1Gb ----------------------------------------------------------------------------------------- Users 600 600 850* 850* ----------------------------------------------------------------------------------------- Disks 64 64 64 64 ----------------------------------------------------------------------------------------- Disk storage (Gbytes) 85 85 85 85 ----------------------------------------------------------------------------------------- Tape drives 8 8 8 8 ----------------------------------------------------------------------------------------- System printers 12 12 12 12 ----------------------------------------------------------------------------------------- I/O Channel multiplexer 4 4 4 4 ----------------------------------------------------------------------------------------- PSI (Bisync and SNA) 8 8 8 8 ----------------------------------------------------------------------------------------- * Larger configurations will be supported in the future. System organization The processor communicates with main memory using the System Memory Bus (SMB). The SMB is a very high-speed bus that provides a 64-bit data path and can support an average data transfer rate of 100 Mbytes per second. The SMB connects to two Central Buses (CTBs) through separate CTB Adapters. Each CTB supports two Channel I/O Buses (CIBs) using separate Channel Adapters. The CIBs support I/O interfaces to peripheral devices and LAN links. See figure 2-5 for the HP 3000 Series 980 system structure. HP 3000 Series 980 Processor. The Series 980 processor, implemented with HP's advanced CMOS VLSI semiconductor technology, is contained on a single board. The Series 980/200 contains two of these processor boards. The processor module includes a single-chip Central Processing Unit (CPU), an Instruction Cache Comparator and Multiplexer (I-CMUX) chip, two Data Comparator and Multiplexer (D-CMUX) chips, an SMB to Processor Interface (SPI) chip, and the Floating-Point Coprocessor (FPC). The very fast 21 ns CPU instruction cycle time is due to the advanced implementation of the CPU, which uses submicron CMOS technology.Figure 2-2. HP 3000 Series 980 Processor HP 3000 Series 955 and 960 processor. The Series 955 and 960 processor module includes a single-chip CPU, a single-chip TLB Control Unit (TCU), two Cache Control Units (CCUs), a single-chip System Interface Unit (SIU), and the Floating-Point Coprocessor. Features comparison 955 960 980/100 980/200 ---------------------------------------------------------------------------------------- Performance x 955 1.0 1.4 2.4 3.7 ---------------------------------------------------------------------------------------- Virtual addressing 48 bit 48 bit 64 bit 64 bit ---------------------------------------------------------------------------------------- CPU cycle time 37 ns 37 ns 21 ns 21 ns ---------------------------------------------------------------------------------------- CPU data cache 128 Kbyte 512 Kbyte 512 Kbyte 2x512 Kbyte ---------------------------------------------------------------------------------------- CPU instruction cache 128 Kbyte 512 Kbyte 512 Kbyte 2x512 Kbyte ---------------------------------------------------------------------------------------- Total cache 256 Kbyte 1 Mbyte 1 Mbyte 2x1 Mbyte ---------------------------------------------------------------------------------------- Pipelining 5 stage 5 stage 5 stage 5 stage ---------------------------------------------------------------------------------------- TLB on CPU chip -- -- 128 2x128 ---------------------------------------------------------------------------------------- External TLB entry 16 K 16 K 8 K 2x8 K ---------------------------------------------------------------------------------------- Cache The CPU cache is a high-speed buffer that significantly increases system performance by minimizing accesses to main memory. Cache access can provide up to an order of magnitude faster access than main memory. Based on a locality algorithm, the system automatically moves into cache the code and data that are most likely to be required. As a result, the required code and data are found in cache almost all the time. Data in the cache is only written to memory when the processor requires more data to be read into cache, when a direct memory access operation is performed, or upon power failure. By providing a large amount of CPU cache, the high-end systems maximize the cache benefits. The larger the CPU cache, the more likely it is that the required data and code will be in cache. Instruction pipelining Instruction pipelining maximizes the use of processor resources by operating on multiple instructions simultaneously, which allows the execution of one instruction each CPU clock cycle. Separate Instruction and Execution Units facilitate instruction pipelining and provide efficient, parallel use of processor resources. The Instruction Unit controls instruction sequencing. It fetches instructions from the Instruction Cache and stores them in the Instruction Register. The Instruction Unit executes branch instructions, maintains processor status, and handles traps and interrupts. The Execution Unit executes all instructions requiring data manipulation. It contains the Arithmetic Logic Unit (ALU) and barrel shifter, which together perform arithmetic, logical, shift, extract, and deposit instructions. The Execution Unit contains 32 general-purpose registers, which store the results of these operations. The Series 955, 960, and 980 all employ a five-stage instruction pipeline. While one instruction is being executed, others are being fetched, and the results of still others are being stored. During the first stage, the instruction is fetched from cache. The instruction is decoded during the second stage, and the resulting CPU internal calculation or function is performed during the third stage. The fourth stage is used to generate the condition code for the corresponding result. Finally, in the fifth stage, a general purpose register is set within the corresponding cache or internal result. The net effect is that except for penalties such as cache misses, one instruction exits the pipeline (completes) every CPU cycle.Figure 2-3. Instruction Pipelining Floating-point coprocessor For scientific, engineering, and statistical applications that require high performance in floating-point calculations, a floating-point coprocessor is standard on Series 955, 960, and 980 systems. The Floating-Point Coprocessor supports single- (32-bit) and double- (64-bit) precision floating-point operands of the ANSI/IEEE 754-1985 standard. The Floating-Point Coprocessor and the CPU operate in parallel, with the CPU performing integer calculations and other functions while the coprocessor performs floating-point calculations. This parallel operation provides a high level of performance for applications that use floating-point calculations. The Floating-Point Coprocessor consists of twelve 64-bit-wide registers for operands and is implemented on two high-speed ECL chips on the Series 955, 960, and 980. The Series 980 provides higher floating-point performance than the Series 955 and 960. In all cases, the Floating-Point Coprocessor is attached to the CPU's cache bus. Virtual memory management The HP 3000 900 Series supports one of the largest address spaces in the industry, which provides tremendous expandability for large applications and data structures. Virtual memory management automatically maps all program and data files into virtual memory, which is many times greater than physical memory. Virtual addresses on the HP 3000 Series 955 and 960 are 48 bits long and are divided into 65,536 spaces, each space being 2 Gbytes. The Series 980 supports 64-bit virtual addresses or over four billion spaces. Each space is further divided into fixed-length, 2-Kbyte pages, which hold data or code. A single data structure can be up to 1 Gbyte or 2 Gbytes in length (compiler-dependent), and program code can span multiple spaces.Figure 2-4. Virtual Memory Organization Virtual address translation Because virtual addresses are much larger than physical addresses, virtual-to-physical address translation is required. A high-speed RAM buffer called the Translation Lookaside Buffer (TLB) optimizes this task. The TLB can be considered to be a table that holds the most recently referenced virtual addresses and their corresponding physical addresses. When a virtual-to-physical address translation occurs, the TLB checks to ensure that the executing process has sufficient authorization to perform the requested read, write, or execute access. Over 99 percent of the time, the needed address is found in the TLB. If the address is not in the TLB, a software hashing scheme is used to find the address of the required code or data in main memory. If the instruction or data is on a page that is not in main memory, a page fault occurs, and the required page is copied from disk. Together, the TLB and hashing scheme provide a very fast and efficient means for retrieving code and data from main memory and disk. Memory subsystem Main memory capacities of the Series 955, 960, and 980 systems are given in the table below. The 16-Mbyte memory array board uses 1-Mbit, fast-page mode dynamic RAMs. The 64-Mbyte board uses 4-Mbit, fast-page mode dynamic RAMs. System Standard memory Maximum memory (Mbytes) Expansion increments (Mbytes) (Mbytes) ---------------------------------------------------------------------------------------- 955 96 256 16 960 128 256 16 980/100 192 512 16 and 64 980/200 256 1024 16 and 64 Main memory has battery backup to ensure that information is maintained for a minimum of 15 minutes in the event of an interruption in AC power. Automatic powerfail allows the operating system to be automatically restarted and processing to continue without data loss upon resumption of power. Error correcting code (ECC) memory is standard on all HP 3000 900 Series systems. The internal memory word size is 72 bits with 64 bits of two 32-bit words and 8 bits for error detection and correction. Single-bit errors are automatically detected and corrected to ensure data integrity. Multibit errors are automatically detected, and a high-priority interrupt is sent to the system software for appropriate action. Memory interleaving The Series 980/200 uses the memory subsystem to implement cache-line interleaving, which improves performance by increasing aggregate bandwidth for usable memory. Two memory controllers are standard on the Series 980. Consecutive cache-lines are fetched from alternate memory modules to improve the effective data return rate, while allowing parallel access to cache-lines on the same page from different processors. Subsystems Buses The wide data paths and fast, synchronous clocking of the high-end system buses provide high-performance I/O throughput. I/O performance is further enhanced because there are multiple paths to I/O devices through up to four adapters and low-level buses.Figure 2-5. HP 3000 Series 980 System Structure System memory bus The System Memory Bus (SMB) is the communication path between the CPU, the main memory, and the CTB Adapters. The SMB provides a 64-bit-wide data path and runs synchronously with a 27.5-MHz clock. It supports an average data transfer rate of 100 Mbytes per second. Central bus adapters The central bus adapters provide the interface between the SMB and the CTB. The CTB Adapters act as transfer agents for direct memory access (DMA) transfers and direct I/O transfers between the channel adapters and the CPU and main memory. The high-end systems come standard with two CTB Adapters. Central bus The central bus (CTB) is the communication path between the CTB adapters and the channel adapters. The CTB provides a 32-bit data path and runs synchronously with a 9.2 MHz clock. It supports sustained data transfer rates of 20 Mbytes per second. In addition, the CTB directly supports a Programmable Serial Interface (PSI) card to provide point-to-point communication between HP 3000 computers and from the HP 3000 to IBM systems using Bisync and SNA. Channel I/O bus adapters The Channel I/O Bus Adapters, or Channel Adapters, for short, provide the interface between the CTB and the CIBs. Each Channel Adapter serves as a high-performance channel multiplexer providing full DMA for all HP-IB, HP-FL, and LAN I/O Channels and synchronizing the different speeds and bandwidths of the CTB and the CIBs. DMA allows large blocks of data to be transferred to and from main memory with minimum CPU intervention, thereby reducing CPU overhead. The high-end systems include two Channel Adapters; a third and fourth Channel Adapter may optionally be added as an option. Channel I/O buses The high-end systems support up to four Channel I/O Buses (CIBs), each supporting up to seven cards for interfacing peripheral devices and providing data communication functions. Each CIB provides a 16-bit-wide, bidirectional data path that runs synchronously with a 4-MHz clock. A significant benefit of having multiple CIBs and Channel Adapters is that this approach provides multiple concurrent paths to I/O devices. Memory-mapped I/O I/O operations are initiated and controlled using a memory-mapped I/O scheme, such that the processor only needs to access reserved virtual or physical memory locations to control I/O operations. Memory-mapped I/O allows for streamlined I/O operations and thus increases system performance in I/O-intensive applications. Peripheral connections Disks are connected using HP Fiber-Optic Link interfaces (HP-FL), each supporting up to 8 disks. Each HP-FL can support a data transfer rate of up to 5 Mbytes per second. Fiber-optics offer exceptional immunity to noise, and HP-FL allows disks to be located up to 500 meters from the SPU. Tapes and printers (as well as disks) are connected using the 8-bit wide, IEEE-488 standard Hewlett-Packard Interface Bus (HP-IB). HP-FL and dual fiber-optic disk drives are required for support of HP Mirrored Disk/XL, a disk shadowing capability, and HP SPU Switchover/XL, an SPU recovery capability.Figure 2-6. HP 3000 S955, S960, and S980 I/O Attachments Workstation and serial connections Connections for workstations, serial printers, and other serial devices are provided using Datacommunications and Terminal Controllers (DTCs), which are distributed over an IEEE 802.3 LAN. This flexible connection scheme allows DTCs to be situated in the departments they serve, saving the cost and effort of running cables from each workstation back to the processor. The DTC48 supports up to 48 direct-connect ports, 36 modem ports, or a combination of the two. The DTC16 supports up to 16 direct-connect ports, 12 modem ports, or a combination of the two. PCs can also be connected to the HP 3000 through HP LAN Manager and Novell NetWare LANs. Physical connections are made using HP EtherTwist, a LAN scheme that uses unshielded twisted pair (or phonewire). Terminal connections are not supported on the standard servers. Instead, all PC workstations are connected to the server using a LAN. Terminal connections can be added to the server by purchasing an additional terminal connection software product. System-to-system data communication HP Network Services provides virtual terminal, network file transfer, remote file and TurboIMAGE database access, network interprocess communication, and remote process management between HP 3000s on an IEEE 802.3 or Ethernet LAN using HP LAN Link/XL, or over wide areas using the HP DTC X.25 Network Link or the HP NS Point-to-Point Link. For system-to-system, point-to-point communication to other HP 3000s and connection to IBM systems using SNA and Bisync, the Programmable Serial Interface (PSI) card is connected directly to the CTB. In multivendor inter-operational environments, the HP 3000 supports ARPA Telnet and File Transfer Protocol (FTP), and OSI X.400 messaging services and File Transfer Access Method (FTAM). HP SNA Link/XL and HP BSC Link/XL are provided for HP-to-IBM system communication in SNA and Bisync environments respectively. Network services over these links include HP SNA IMF/XL for SNA 3270 emulation; HP SNA NRJE/XL for SNA remote job entry; HP LU6.2 API, an LU6.2 program-to-program application interface; HP SNA Distributed Host Command Facility/XL (HP SNA DHCF/XL) for IBM 3270/PC access to the HP 3000; and BSC RJE/XL for Bisync remote job entry. For detailed network information, please refer to Chapter 5,"Networks". Environmental Specifications -------------------------------------------------------------------------------------- AC input voltage (nominal) 208 VAC, three phase @ 60 Hz 380 VAC, three phase @ 50 Hz 415 VAC, three phase @ 50 Hz -------------------------------------------------------------------------------------- Input voltage tolerance +- 10% from nominal -------------------------------------------------------------------------------------- Input current 8.0 amps @ 208 VAC 60 Hz 4.4 amps @ 380 VAC 50 Hz 4.0 amps @ 415 VAC 50 Hz -------------------------------------------------------------------------------------- Heat dissipation, maximum 7900 BTU/hr -------------------------------------------------------------------------------------- Physical dimensions Height: 991 mm (39 in.) Width: 1296 mm (51 in.) Depth: 711 mm (28 in.) Weight: 400 Kg (880 lb) -------------------------------------------------------------------------------------- Operating temperature, system 20 degrees to 25.5 degrees C (68 degrees to 78 degrees F) -------------------------------------------------------------------------------------- Relative humidity, system (operating) 40 to 60% (noncondensing) -------------------------------------------------------------------------------------- Altitude (operating) Up to 4572 m (15,000 ft) -------------------------------------------------------------------------------------- Battery backup time, minimum 15 minutes -------------------------------------------------------------------------------------- Acoustics 7.3 Bels sound power (A) --------------------------------------------------------------------------------------
![[FFN7]](../../pic3k/M011943/FFN7.gif)
![[FFN8]](../../pic3k/M011943/FFN8.gif)
![[FFN9]](../../pic3k/M011943/FFN9.gif)
![[FFN10]](../../pic3k/M011943/FFN10.gif)
![[FFN11]](../../pic3k/M011943/FFN11.gif)
![[FFN12]](../../pic3k/M011943/FFN12.gif)