PPT Slide
N-Class Block Diagram.“IA-64 Ready”
Memory Controller
I/O Controller
Bus Converter
PA-8500 CPU
PA-8500 CPU
Bus Converter
PA-8500 CPU
PA-8500 CPU
Bus Converter
PA-8500 CPU
PA-8500 CPU
Bus Converter
PA-8500 CPU
PA-8500 CPU
IA-64 Chipset
SDRAM SIMS
7.6Gb/Sec
130ns Latency
32w Interleave
Aggregate Bandwidths
System Bus: 3.8Gb/Sec
Memory Bus: 7.6Gb/Sec
I/O Bus: 5.8Gb/Sec
2.9Gb/Sec
2.9Gb/Sec
IA-64 Bus 1 1.9Gb/Sec
IA-64 Bus 0 1.9Gb/Sec
I/O Controller
Previous slide
Back to first slide
View graphic version
Author
|
Title
|
Track
|
Home
Send email to Interex
or to the
Webmaster
©Copyright 1999
Interex
. All rights reserved.